Self-Checking State Machine Realization in CMOS.
Progress rept. 1 Jul-31 Dec 94,
NORTH CAROLINA AGRICULTURAL AND TECHNICAL STATE UNIV GREENSBORO DEPT OF ELECT RICAL ENGINEERING
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In this reporting period we have accomplished the following i Developed a procedure for totally self-checking TSC checker design for m-out-of-2m codes at the transistor level. ii Derived a technique for designing TSC fault-tolerant systems.
- Electrical and Electronic Equipment