An Architecture Study of a Byzantine-Resilient Processor Using Authentication
AIR FORCE INSTITUTE OF TECHNOLOGY WRIGHT-PATTERSON AFB OH WRIGHT-PATTERSON AFB
Pagination or Media Count:
This architecture study provides the ground work for implementing a new generation of Byzantine resilient processors using authentication. The use of authentication allows a significant reduction in the theoretical requirements necessary for providing Byzantine resilience, or the ability to continue correct operation in the presence of arbitrary or even malicious faults. This decrease in requirements led to a goal of providing a system which combines the stringent standards embodied by Byzantine resilience with the lower costs necessary to make the system viable for more markets than previous Byzantine resilient processors. A layering scheme is proposed which can be placed between the user and hardware. These layers consist of protocols which provide the basic building blocks of the architecture. The proposed authentication protocol which provides the digital signatures used to verify the origin and contents of messages is a public-key protocol using 32-bit Cyclic Redundancy Codes CRCs to encode the message with 32-bit modular inverse key pairs to sign and authenticate the CRC. An interactive consistency protocol responsible for correctly distributing single-source data between processors is built using the SMm algorithm from LSP82 with improvements suggested in Dol83. A voting protocol responsible for generating a group consensus value guaranteed to be the same on all nonfaulty processors suggests exchanging unsigned messages and then using a fun-set majority vote choice function to calculate the group consensus value.