Software Cache Coherence for Large Scale Multiprocessors
ROCHESTER UNIV NY DEPT OF COMPUTER SCIENCE
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Shared memory provides an attractive and intuitive programming model that makes good use of programmer time and effort. Shared memory however requires a coherence mechanism to allow caching for performance and to ensure that processors do not use stale data in their caches. We evaluate several algorithmic and architectural alternatives in the design space of NCC-NUMA machines with a globally-accessible physical address space. We present a new adaptive algorithm for software cache coherence that reduces interprocessor communication and scales to large numbers of processors we compare it to existing software and hardware coherence schemes. We also evaluate the tradeoffs among various write policies write-through, write-through with a write-collect buffer and the effect on performance of using remote memory access. Finally, we observe that certain simple program changes can greatly improve performance. For example, we find that the use of reader-writer locks, synchronization variable relocation, and data structure padding and alignment can allow a protocol to avoid significant amounts of coherence overhead.
- Computer Programming and Software