Accession Number:

ADA281028

Title:

Verification of Arithmetic Functions with Binary Moment Diagrams

Descriptive Note:

Corporate Author:

CARNEGIE-MELLON UNIV PITTSBURGH PA DEPT OF COMPUTER SCIENCE

Personal Author(s):

Report Date:

1994-05-31

Pagination or Media Count:

42.0

Abstract:

Binary Moment Diagrams BMDs provide a canonical representations for linear functions similar to the way Binary Decision Diagrams BDDs represent Boolean functions. Within the class of linear functions, we can embed arbitrary functions from Boolean variables to real, rational, or integer values. BMDs can thus model the functionality of data path circuits operating over word level data. Many important functions, including integer multiplication, that cannot be represented efficiently at the bit level with BDDs have simple representations at the word level with BMDs. Furthermore, BMDs can represent Boolean functions with around the same complexity as BDDs. We propose a hierarchical approach to verifying arithmetic circuits, here basic building blocks are first shown to implement a word-level specification. The overall circuit functionality is then verified at the word level. Multipliers with word sizes of up to 62 bits have been verified by this technique. Formal verification, Binary decision diagrams, Arithmetic circuits, Multipliers.

Subject Categories:

  • Computer Programming and Software

Distribution Statement:

APPROVED FOR PUBLIC RELEASE