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Fault Tolerance in Opto-electronic Computing.
CALIFORNIA UNIV DAVIS DEPT OF ELECTRICAL AND COMPUTER ENGINEERING
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This project has gotten some recognition in both fault modeling and testing of optical interconnects in a opto-electronic system. In the first part, we want to develop a new methodology for performance analysis of opto-electronic systems at a higher level. Our approach is to first identify possible failures in such interconnect implementations, and then extract information from the physical configuration and relate to the system performance parameters. In this way, system-level performance degradation can be estimated to construct design constraint for physical systems. In the second part on testing, we proposed an architecture which integrates the concept of concurrency and distributed test pattern generation for testing complex circuits on a planar layout.
APPROVED FOR PUBLIC RELEASE