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Accession Number:
ADA280065
Title:
Prototype Rule-Based Reliability Analysis for VLSI Circuit Design
Descriptive Note:
Final rept. Oct 1992-Oct 1993
Corporate Author:
ILLINOIS UNIV AT URBANA COORDINATED SCIENCE LAB
Report Date:
1994-04-01
Pagination or Media Count:
82.0
Abstract:
This report describes the development and application of parametric and geometry based macro-models of hot-carrier induced dynamic degradation in MOS VLSI circuits. Previously, a simulation based approach has been used for reliability analysis, but this is inefficient for reliability assessment of very large scale integrated circuits. Geometry-based macro-models for hot-carrier reliability estimation have been developed. The macro-models express hot-carrier damage as functions of designable parameters such as transistor size W, output loading capacitance C1 and the input signal slew rate a. A prototype rule- based reliability diagnosis tool, iRULE, has been developed. This tool uses the macro-models for designing hot-carrier resistant circuits without the need for transient reliability simulations. This provides the ability to analyze very large circuits with more than one million transistors on a workstation in a short amount of time. This report also describes a fast timing reliability simulation tool, ILLIADS-R, that can accurately estimate hot-carrier degradation while providing several orders of magnitude speed up over traditional transistor-level circuit simulators. Reliability, Hot-carrier degradation, VLSI CMOS Circuits, Simulation.
Distribution Statement:
APPROVED FOR PUBLIC RELEASE