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Design of Free Space Interconnected Signal Processor.
Final technical rept. Apr 91-Feb 93,
RUTGERS - THE STATE UNIV NEW BRUNSWICKNJ HILL CENTER FOR THE MATHEMATICAL SCIENCES
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Progress is described on a collaborative effort between the Photonics Center at Rome Laboratory RL, Griffiss AFB and Rutgers University, through the RL Expert Science and Engineering ESE program. The goal of the effort is to develop a prototype random access memory RAM that can be used in a signal processor for a computing model that consists of cascaded arrays of optical logic gates interconnected in free space with regular patterns. The effort involved the optical and architectural development of a cascadable optical logic system in which microlaser pumped S-SEED devices serve as logic gates. At the completion of the contract, two gate-level layouts of the module were completed which were created in collaboration with RL personnel. The basic layout of the optical system has been developed, and key components have been tested. The delayed delivery of microlaser arrays precluded completion of the processor during the contract period, but preliminary testing was made possible through the use of other microlaser devices. Optical computing, Photonic switching, Birefringence, Optical interconnects, SEED.
APPROVED FOR PUBLIC RELEASE