Accession Number:

ADA275108

Title:

Real-Time Data Filtering and Compression in Wide Area Simulation Networks

Descriptive Note:

Technical rept.,

Corporate Author:

UNIVERSITY OF CENTRAL FLORIDA ORLANDO DIV OF SPONSORED RESEARCH

Personal Author(s):

Report Date:

1992-10-02

Pagination or Media Count:

74.0

Abstract:

We present a new memory based CODEC architecture to design a special purpose hardware for real-time multibit compressiondecompression of binary data. The proposed architecture is based on a novel idea of mapping the decodingencoding tree of any variable length binary code on to a memory device that corresponds to simultaneous decodingencoding of multiple bits. The hardware is programmable, easily adaptable and yields a high compression rate. A prototype 2-micron VLSI chip based on this architectural idea has been designed. This chip occupies a silicon area of 6.9 x 6.8 square millimeters and it contains 49,695 transistors with estimated compression rate of 88 Mbitssec and a decompression rate of 53 Mbitssec with a clock rate of 50 MHz. The algorithms have been tested with different types of variable-length binary codes including the JPEG baseline compression scheme. CODEC, Compression, Decompression, JPEG, Multibit data compressiondecompression, Tree based code, Reverse code, Reverse binary tree, Memory map, Perfect map, Contiguous binary superstring, CBS.

Subject Categories:

  • Computer Systems
  • Computer Systems Management and Standards

Distribution Statement:

APPROVED FOR PUBLIC RELEASE