Parallel Built-In Self Test and Pipelined Test Scheduling for Multichip Modules
CALIFORNIA UNIV SAN DIEGO LA JOLLA DEPT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES
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The development of an easily testable multi-chip module is conflicted by the need for denser and faster circuits. We examine the organization of parallel built-in testers for MCMs and its pipelined test scheduling schemes to achieve high test coverage and less testing time at a reasonable area overhead. It is proven the aliasing probability of pipelined multiple-stage parallel signature analysis is of the same magnitude as that of single-stage signature analyzer. As the data width gets higher than 16 bits as that in the MCMs, this parallel and pipelined self-testing approach is favored for both processor and interconnect failure detection.
- Electrical and Electronic Equipment
- Computer Programming and Software