A New Framework for Designing BIT Multichip Modules with Pipelined Test Strategy
CALIFORNIA UNIV SAN DIEGO LA JOLLA DEPT OF ELECTRICAL AND COMPUTER ENGINEERING
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In this paper, a novel test strategy, the Loop Testing Architecture LTA is introduced to reduce aliasing probability and testing time for multichip modules. This is accomplished by connecting Cascadable Built-In Testers CBITs in neighboring pipelined stages to increase the length of the test suites. Fundamental properties of LTA supporting the randomness in the generated test patterns state coverage and the asymptotic aliasing probability are presented. Our results on two small-scale multi-processor configurations show that the aliasing probability in analyzing signatures compared to that of a MLFSR is comparable but with fairly low area overhead, and when compared with the Circular Self-Test Path technique, less testing time is required by LTA. Further evaluation on the potential capabilities provided by the LTA, compared with boundary scan and other pipelined test scheduling approaches confirmed that LTA provides a new framework for designing effective testable systems.
- Electrical and Electronic Equipment
- Manufacturing and Industrial Engineering and Control of Production Systems