Accession Number:

ADA261975

Title:

A Single-Transistor Memory Cell and Sense Amplifier for a Gallium Arsenide Dynamic Random Access Memory

Descriptive Note:

Master's thesis

Corporate Author:

NAVAL POSTGRADUATE SCHOOL MONTEREY CA

Personal Author(s):

Report Date:

1992-12-01

Pagination or Media Count:

98.0

Abstract:

This thesis presents the design and layout of a Gallium Arsenide GaAs Dynamic Random Access Memory DRAM cell. Attempts have been made at producing GaAs DRAM cells, but these have dealt with modifications to the fabrication process, are expensive, and have met with little success. An eight- address by one-bit memory is designed, simulated, and laid out for a standard GaAs digital fabrication process. Three different configurations of RAM cells are considered the Three-Transistor RAM Cell, the One-Transistor RAM Cell with a Diode, and the One-Transistor RAM Cell with a capacitor. All are tested and compared with the circuit simulator HSPICE. The chosen DRAM design uses the One- Transistor RAM Cell with a parallel plate capacitor and a five-transistor differential sense amplifier that handles reading as well as refresh of the memory cells. The differential sense amplifier compares a dummy cell with a memory cell to perform a read. The required timing is presented and demonstrated with read, write, and refresh cycles. Actions to minimize charge leakage are also considered and discussed. The design is simulated for access rates of approximately five nanoseconds, but the basic design can work at much faster rates with little modification.

Subject Categories:

  • Electrical and Electronic Equipment
  • Computer Hardware

Distribution Statement:

APPROVED FOR PUBLIC RELEASE