Accession Number:

ADA261010

Title:

An Investigation of Memory Latency Reduction Using an Address Prediction Buffer

Descriptive Note:

Master's thesis

Corporate Author:

NAVAL POSTGRADUATE SCHOOL MONTEREY CA

Personal Author(s):

Report Date:

1992-12-01

Pagination or Media Count:

39.0

Abstract:

Developing memory systems to support high-speed processors is a major challenge to computer architects. Cache memories can improve system performance but the latency of main memory remains a major penalty for a cache-miss. A novel approach to improve system performance is the use of a memory prediction buffer. The memory prediction buffer MPB is inserted between the cache and main memory. The MPB predicts the next cache-miss address and pre-fetches the data. The use of an MPB in a computer system is shown to decrease main-memory latency and increase system performance .... Memory latency, Computer architecture, Cache memory, Computer performance, Latency reduction, Cache hierarchy.

Subject Categories:

  • Computer Hardware

Distribution Statement:

APPROVED FOR PUBLIC RELEASE