Reconfiguration Schemes for Fault-Tolerant Processor Arrays
Final rept. 1 Jul 1988-31 Aug 1992
PURDUE UNIV LAFAYETTE IN
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This project addressed several aspects of the problem of designing highly-reliable dynamically reconfigurable processor arrays. The proposed work focused mainly on reconfiguration schemes required to implement fault-tolerant processor arrays. According to the original statement of work, the following complementary objectives were pursued 1 a methodology for the design and evaluation of processor-switched arrays. 2 a methodology for the design and evaluation of multi-level hierarchically reconfigurable processor arrays. 3 a methodology for the design of fault-tolerant interconnection routers for processor arrays with decentralized routing control, and 4 algorithm reconfiguration strategies which, together with hardware reconfiguration schemes, can be used to achieve graceful degradation in processor arrays. The emphasis of the proposed research was on the development of optimal reconfiguration schemes for each of the above objectives by using mathematical and simulation tools. For this purpose, evaluation methods and adequate measures were also studied and developed. These measures include not only reliability but also joint measures of performance, hardware area and reliability.
- Computer Hardware