Scan-Based Switching Tests
Final technical rept.
HARRIS CORP MELBOURNE FL GOVERNMENT INFORMATION SYSTEMS DIV
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This report describes an algorithm for generating scan-based switching tests. The only design consideration required by this algorithm, besides the scan design is the capability to execute two functional clocks with a desired interval between logic scans. The algorithm generates a test vector which is scanned in to cause the source register of the delay path to toggle on the first clock, and captures a transition at the output register of the delay path on the second clock. The algorithm also identifies paths that are not testable, and identifies the points of conflict.
- Test Facilities, Equipment and Methods