Accession Number:

ADA257334

Title:

Temperature Distribution and Thermally Induced Stresses in Electronic Packages

Descriptive Note:

Master's thesis

Corporate Author:

NAVAL POSTGRADUATE SCHOOL MONTEREY CA

Personal Author(s):

Report Date:

1992-09-01

Pagination or Media Count:

104.0

Abstract:

This investigation is concerned with the steady state temperature and thermally induced stress distributions in electronic packages due to heat generated by the chip. Finite Element codes were employed to solve for the distribution of temperature and stresses within the package. Four parametric studies were undertaken to determine their effects on system behavior. The material study considered two chip and two solder materials and four substrate materials. Convective heat transfer was varied from 200 WM2 deg C through 500 WM2 deg C. In the geometric study, chip height to overall height was varied. The effect of package encapsulation was studied. Results are presented for both temperature and stress distributions at the solder interfaces. Thermoelastic stresses, Tri-material package.

Subject Categories:

  • Electrical and Electronic Equipment
  • Thermodynamics

Distribution Statement:

APPROVED FOR PUBLIC RELEASE