A Pipelined, High-Precision FFT Architecture
MITRE CORP BEDFORD MA
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This paper presents a highly-integrated, high-precision FFT architecture. A 1.2 um CMOS implementation of this architecture has yielded a 32-bit, 64K-point FFT that operates at a continuous 4-million-samples-per-second data rate. All FFT support functions, including coefficient generation and memory interfacing, are included on-chip. FFT architecture, CMOS implementation.
- Computer Hardware