Accession Number:

ADA257108

Title:

A Technique for Predictable Real-Time Execution in the AN/UYS-2 Parallel Signal Processing Architecture

Descriptive Note:

Master's thesis

Corporate Author:

NAVAL POSTGRADUATE SCHOOL MONTEREY CA DEPT OF ELECTRICAL AND COMPUTER ENGINEERING

Personal Author(s):

Report Date:

1991-12-01

Pagination or Media Count:

141.0

Abstract:

The ANUYS-2 provides the Navy with a state of the art Digital Signal Processor. The ANUYS-2 is programmed utilizing the Processing Graph Methodology PGM, which represents specific tasks as nodes in a graph. It utilizes a simple first-come-first-served FCFS run-time resource allocation mechanism that supports large-grain data flow processing. While the mechanism is robust, easy to implement, and results in low runtime overhead, it is difficult to predict if a given PGM will meet the application requirements. Therefore, an approach that uses compile-time analysis to exploit the periodic arrival of data and a priori knowledge of the amount of computation and communication overhead is investigated. Improvement in performance of the machine when the PGM graphs are restructured using this approach, called Revolving Cylinder scheduling, is observed and it is found to be effective when there is a high communication overhead or when the PGM nodes are of uniform size.

Subject Categories:

  • Computer Hardware

Distribution Statement:

APPROVED FOR PUBLIC RELEASE