Aspects of a Parallel-Architecture Simulator
MASSACHUSETTS INST OF TECH CAMBRIDGE LAB FOR COMPUTER SCIENCE
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This thesis discusses the use of code augmentation in PROTEUS, a high-performance parallel-architecture simulator. PROTEUS multiplexes a single processor among the various activities in a simulated parallel machine to provide accurate information about the timing and behavior of an application and the underlying simulated architecture. PROTEUS is fast, accurate, and flexible it is one to two orders of magnitude faster than comparable simulators, it can reproduce results from real multiprocessors, and it is easily configured to simulate a wide range of MIMD architectures. Traditional multiprocessor simulators simulate the machine cycle by cycle, interpreting each instruction. The high overhead of instruction interpretation makes these simulators too slow for research in the area of parallel systems. PROTEUS simulates most instructions via a combination of direct execution and code augmentation, which reduces the simulation overhead for these instructions by roughly a factor of one hundred. In addition to performance, code augmentation offers several other benefits for multiprocessor simulators, such as nonintrusive profiling and stack overflow detection. Primary among these benefits is precise control of the cost in machine cycles of a piece of code. The ability to assign code a cost of zero cycles allows users to generate nonintrusive monitoring and debugging code. Because the monitoring code costs zero cycles, it has no effect on the timing of the simulation. Thus, users can add arbitrary monitoring and debugging code without interfering with the simulation. The ability to assign costs also allows users to tune costs to match a particular architecture, thus increasing the accuracy of the simulation.
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