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Real-Time Adaptive Sidelobe Canceller Architectures and Implementations

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A programmable, reconfigurable digital signal processing DSP array has been designed in response to the need for a real-time adaptive sidelobe canceller to support wide-bandwidth high-frequency HF radar concepts. These concepts incorporate multiple up to 128 main beams and many degrees of freedom by using many auxiliary antenna elements, and employ frequency sub-banding to partition a 1 MHz instantaneous bandwidth. The real-time sidelobe canceller is based on the Gram-Schmidt orthogonalization procedure and uses concurrent block adaptation to derive an optimal solution for the available data. The sidelobe canceller implementation configures the modular DSP array into a two-dimensional Gram-Schmidt processor. A proof-of-concept sidelobe canceller implementation will be able to perform sidelobe cancellation on two simultaneous main beams using eight auxiliary channels. The DSP array sidelobe canceller can be expanded to use over 40 auxiliary channels to support over 128 main beams. The array consists of TMS32OC30-based processing nodes that provide four independent data ports two inputs and two outputs connected via high-speed serial data links that sup port 2-megaword-per-second sustained throughput rates 8-megaword-per-second burst rates. These manually configured data connections are separated from the control structure, allowing a variety of interconnection strategies one- dimensional, two-dimensional, ring, etc.. A host processor is used to download application code and control the system. This programmable, reconfigurable array processor can also be used for a variety of other applications, including the singular value decomposition matrix-matrix multipliers, and frequency and transforms.

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  • Lasers and Masers

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