VLSI for High-Speed Digital Signal Processing
Quarterly progress rept. 1 Apr-30 Jun 1992,
CALIFORNIA UNIV LOS ANGELES
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During the present quarter we have made some architectural changes to the five-processor ring-structured programmable digital filter IC to improve the system performance. The main change is to insert a register between the coefficient RAM and the multiplier to eliminate the read time of the RAM from the critical path of the multiplier. This provides a substantial improvement in the system performance since the critical path of the multiplier determines the performance of the over-all five-processor system. Figure 1 shows a block diagram of the new ALU architecture. A TinyChip comprising the multiplier with the redesigned carry-select vector-merge adder described in the previous report has been sent to MOSIS for fabrication. The IC consists of the 12-bit by 11-bit multiplier, the coefficient and data input registers, the output register, and RAM to store the coefficient and input data. The multiplier itself consists of 3100 transistors occupying an area of 1.53 mm2 1.313 mm by 1.166 mm in 2- micron CMOS technology and is simulated to operate in 22 ns. We expect the prototype parts in the middle of the next quarter for testing. Figure 2 shows the architecture of the TinyChip submitted for fabrication and Figure 3 shows the layout of this IC.
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