Accession Number:

ADA248087

Title:

Hardware-Verification Through Logic Extraction

Descriptive Note:

Doctoral thesis

Corporate Author:

AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH SCHOOL OF ENGINEERING

Personal Author(s):

Report Date:

1992-03-01

Pagination or Media Count:

166.0

Abstract:

A Prolog-based system is described which employs logic-extraction to perform hardware-verification. The extraction rules are built automatically from hierarchical structural VHDL models, enabling the equivalence of a structural VHDL description and a layout specification to be verified. Pin-to-pin critical- path analysis is performed within the logic-extraction process many noncritical paths are pruned early, making pin-to-pin critical path analysis of large circuits feasible. It is demonstrated that a design methodology based on logic extraction, VHDL, and a layout tool can provide a fabricated functionally- correct IC design without circuit-level or switch-level simulation. This methodology is shown to be practical for VLSI designs up to 250,000 transistors in size. The properties of correctness, completeness, and guaranteed termination are examined for the extraction process. VLSI, VHDL, Prolog, Circuit Extraction, Reverse Engineering, Computer Aided Design, Integrated Circuits, Artificial Intelligence.

Subject Categories:

  • Computer Systems Management and Standards

Distribution Statement:

APPROVED FOR PUBLIC RELEASE