VHDL and Waves Descriptions for a Pseudo-Random Pattern Generator
Final rept. 5 Apr-28 Oct 1991
WRIGHT LAB WRIGHT-PATTERSON AFB OH
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A VHDL model for a 32-bit linear feedback shift register is documented, along with a WAVES dataset that provides test vectors for it. The register operates with a leading-edge dual clock, an asynchronous reset, and control bits to enable shifting to the right and loading. Other inputs are a polynomial and a seed value the output is a bit pattern. The feedback feature is controller by the polynomial. For each polynomial bit position with a value of 1, the value of the register corresponding to that is fed through feedback before being shifted. The WAVES dataset is used to generate input test vectors for the register, and to provide a utility to compare actual outputs to predicted outputs. There are three different architectures for the register structural behavioral, and structural with multiple component instantiations produced by the VHDL generate statement. There are also two architectures for the test bench one that uses the WAVES dataset, and one that produces input vectors internally. The WAVES test bench uses a built-in utility to check outputs from each of the three register architectures against each other, and the non-WAVES test bench does these checks internally.
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