Asynchronous Design for Parallel Processing Architectures
Semiannual rept. Jul-Dec 91,
STANFORD UNIV CA
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The objective of this research is to provide a design methodology for connecting heterogeneous hardware modules that have inherently different functional and timing behavior. With the constraints dictated by the system- level interaction, we need to adopt a modular design approach without compromising the global performance. The main task of this effort will be the development of the theory for optimal interface circuits synthesis from high- level specification, with emphasis on testability and performance. In July-Dec 1991 we have concentrated on the gate-level synthesis of asynchronous control circuits and introducing timing information into the synthesis process to increase circuit performance.
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