Accession Number:

ADA244182

Title:

Formalization and Validation of an SADT Specification Through Executable Simulation in VHDL

Descriptive Note:

Master's thesis,

Corporate Author:

AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH SCHOOL OF ENGINEERING

Personal Author(s):

Report Date:

1991-12-01

Pagination or Media Count:

314.0

Abstract:

Formalizing an informal requirements specification, such as SADT, and executing the formal specification in a simulation environment, such as VHDL, provides a requirements analyst a means to validate the behavior of a specification early in the development life cycle. This research effort investigated and demonstrated the feasibility and benefit of transforming an SADT specification of a system into an equivalent VHDL executable simulation. Both non-time related behavior and concurrent, real-time related behavior is addressed. First, a decision table extension to SADT is created so that detailed, executable behavior can be specified. Next a mapping from SADT to VHDL is defined. Last, this mapping was applied to two example problems the Heating System and the Lift elevator Control System. An SADT specification was generated for each of these problems, and the resulting specification was transformed into an equivalent VHDL specification using the mapping technique defined by this research. The VHDL simulation environment was used to execute the specification, determine its behavior, make necessary changes, and re- execute the specification until the proper system behavior was specified.

Subject Categories:

  • Computer Programming and Software

Distribution Statement:

APPROVED FOR PUBLIC RELEASE