Fault Tolerant Architectures for Multiprocessors and VLSI-Based Systems
Final rept. 1 May 1988-29 Sep 1991,
MASSACHUSETTS UNIV AMHERST DEPT OF ELECTRICAL AND COMPUTER ENGINEERING
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A general framework for shift register-based test response compressors was developed based on algebraic coding theory. It has advantages over Markov modeling in allowing exact computation of aliasing probability and extension to other forms of built-in self-test. The use of deBruijn graphs was adopted to studies of VLSI-based multiprocessor networks. These allowed derivation of lower bounds on VLSI layout areas and provided a method to meet those bounds. The graphs were extended to hyper-de Bruijn networks. Finally a design was produced for fault-tolerant testable RAMs TRAMs.
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