A Prolog System for Converting VHDL-Based Models to Generalized Extraction System (GES) Rules
Final rept. Jun-Dec 1990
AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH
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With the advent of VHDL accurate documentation of hardware designs is a practical reality. In the past, schematics were typically used for documentation of hardware designs. However, these schematics would usually become obsolete as the hardware design was being constructed. Deviations in the hardware design would sometimes not be reflected in the schematics. For design groups, failure to update schematics could lead to different parts of a hardware design becoming incompatible. A system to ensure compliance of hardware with its VHDL documentation is presented in this paper. The system, vhdl2ges, is meant to help guide the development of hardware by pointing out where hardware deviates from its VHDL documentation. A tool is used to parse the VHDL description into a Prolog-type intermediate form. A customized GES is constructed that checks a netlist derived from a layout description for deviations from the components and interconnections specified in the structural VHDL documentation.
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