Testing the One-Port Random Access Memory (1PRAM) Module of TRW's CPUAX Signal Processing Superchip
NAVAL RESEARCH LAB WASHINGTON DC
Pagination or Media Count:
The CPUAX Signal Processing Superchip has been developed by TRW under the VHSIC Phase II program. The chip utilizes a 0.5 um Complementary Metal Oxide Semiconductor process and achieves a maximum throughput of 200 Mflops. The chip consists of 61 active macrocells, including 2 floating point arithmetic logic units ALUs, 2 multiply accumulators MACs, read and write address generators, 6 storage elements, read and write memory interfaces, and 39 identical 4Kx1-bit one port random access memory 1PRAM modules. Each macrocell is provided with a chip specification and an IEEE 1076 VHSIC Hardware Description Language VHDL functional model. This report describes the testing of the functional performance and VHDL model of the 1PRAM macrocell by NRL. Testing was performed for two reasons to verify that the macrocell behaves as specified and to validate the VHDL model. Three 1PRAM macrocells were received, each mounted on a 28-pin DIP test chip. All testing described herein was carried out on a Daisy Megalogician connected to a Physical Modeling Extension PMX using the 5.03 version of the Daisy DNIX operating system. This report describes the testing procedures, the problems encountered, and the ramifications of these. An algorithm is also included for future testing of similar devices on the Daisy CAD system with use of the PMX. It is shown that the 1PRAM functioned as TRW described in tis design publications, which can be found in the References. However, the test vectors provided by TRW, which were delivered with the VHDL model, did not activate the chip as expected. This VHDL model was also shown to be invalid.
- Electrical and Electronic Equipment
- Computer Programming and Software