Accession Number:

ADA231364

Title:

Integrated Data and Control Level Fault Tolerance Techniques for Signal Processing Computer Design

Descriptive Note:

Rept. for 1 Jul 1988-30 Sep 1990,

Corporate Author:

CALIFORNIA UNIV DAVIS DEPT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE

Personal Author(s):

Report Date:

1990-09-01

Pagination or Media Count:

62.0

Abstract:

High Speed linear signal processing in digital systems is protected efficiently by algorithmic fault-tolerance employing real block or convolutional codes. The main signal processing operation functions normally while parity samples derived from the input data are compared against corresponding parity associated with the output samples. The parity computations and comparisons providing error detection are performed in parallel with the normal signal processing, guaranteeing no speed degradation. Real block codes are used to protect processing finite length input and output segments whereas real convolutional codes are natural for protecting a continuous input and output streams of samples. The corresponding parity values are compared considering difference threshold to account for numerical roundoff and quantization effects. A mean-square error criterion is used in analyzing the parity comparison process. Errors due to temporary and permanent hardware failures as well as numerical roundoff and quantization noise are allowed simultaneously in the main processing system, and the parity calculation and comparison subassemblies.

Subject Categories:

  • Computer Programming and Software

Distribution Statement:

APPROVED FOR PUBLIC RELEASE