Accession Number:

ADA231320

Title:

Implementation of FFT and Pulse Compression Routines on the SPT frequency Domain Array Processor

Descriptive Note:

Corporate Author:

DEFENCE RESEARCH ESTABLISHMENT OTTAWA (ONTARIO)

Personal Author(s):

Report Date:

1990-09-01

Pagination or Media Count:

58.0

Abstract:

The Frequency Domain Array Processor FDAP is a VME compatible circuit board built by Signal Processing Technologies SPT. The FDAP can process integer data arrays containing up to 8192 32 bit complex words or 1684 16 bit real words. It is capable of 400 Million Operations Per Second MOPS with a maximum InputOutput IO rate of four billion bits per second. It also has a double buffered memory architecture permitting IO transfers to occur in parallel with data processing. The FDAP can be hosted by an IBM PCAT-compatible computer using a bus adaptor interface available from BIT3 Computer Corp. The FDAP board is based upon SPTs DASPPAC chip set. This chip set and the varios system architectures which can be built around it are reviewed. The FDAP board and its associated development system are also reviewed. The ease of implementation of typical radar signal processing functions on the FDAP board are then examined. Fast Fourier Transform and pulse compression routines are implemented via a supplied user interface as well as a high level language C. The results are examined and comments on the FDAP and its associated system development tools are made.

Subject Categories:

  • Electrical and Electronic Equipment
  • Computer Programming and Software
  • Active and Passive Radar Detection and Equipment

Distribution Statement:

APPROVED FOR PUBLIC RELEASE