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Computer Aided Design Tools and Algorithms for Submicron Technologies

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Final rept. 1 Jul 1987-30 Jun 1990

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Advanced algorithms for two and three dimensional modeling of semiconductor devices have been developed, implemented on parallel computers and tested using several high performance technologies. Computational limitations for semiconductor device analysis have been extended to greater than 100000 nodes and speedup factors greater than 10-fold have been realized using distributed memory MIMD architectures. Two classes of algorithms have been explored using parallel processing-distributed multifrontal DMF and Monte Carl MC. The DMF algorithm has been implemented and tested for 3D device analysis of MOS, bipolar and latchup examples using iterative methods for single- and two-carrier transport. A windowed MC analysis of 2D hot carrier effects in Si MOS and GaAs MESFET devices has been achieved on several parallel architectures with near ideal speedup factors up to 20 processors. Usability of device simulation has been enhanced and demonstrated through applications. The range of technologies that can be modeled with the 2D PISCES program now includes GaAs, GeSi heterojunctions and photo-and other carrier-generation process. Moreover, layout-driven input 2D3D output visualization capabilities increase user efficiency. Device and technology scaling applications have been used to evaluate both 2D and 3D device capabilities. BiCMOS scaling issues and new structures have been evaluated using PISCES and mixed-mode device circuit capabilities. Broad use of this work both in industry and government has been demonstrated. The 3D prototype code STRIDE has been to analyze CMOS latchup. Industrial interest in this code has resulted in State of California support to move the prototype into commercial development.

Subject Categories:

  • Electrical and Electronic Equipment
  • Computer Hardware

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