Accession Number:

ADA231006

Title:

Test Generation for Digital Circuits Using Parallel Processing

Descriptive Note:

Final rept. Jun 1989-Jun 1990,

Corporate Author:

SYRACUSE UNIV NY SCHOOL OF COMPUTER AND INFORMATION SCIENCE

Report Date:

1990-12-01

Pagination or Media Count:

71.0

Abstract:

The problem of test generation for digital logic circuits is an NP-Hard problem. Recently, the availability of low cost, high performance parallel machines has spurred interest in developing fast parallel algorithms for computer-aided design and test. This report describes a method of applying a 15-valued logic system for digital logic circuit test vector generation in a parallel programming environment. A concept called fault site testing allows for test generation, in parallel, that targets more than one fault at a given location. The multi-valued logic system allows results obtained by distinct processors andor processes to be merged by means of simple set intersections. A machine-independent description is given for the proposed algorithm.

Subject Categories:

  • Electrical and Electronic Equipment
  • Computer Hardware

Distribution Statement:

APPROVED FOR PUBLIC RELEASE