Accession Number:

ADA230396

Title:

A Generalized Extraction System for VLSI

Descriptive Note:

Final rept. Jul 1987-Aug 1990,

Corporate Author:

WRIGHT RESEARCH AND DEVELOPMENT CENTER WRIGHT-PATTERSON AFB OH

Report Date:

1990-10-01

Pagination or Media Count:

110.0

Abstract:

A Generalized Extraction System for VLSI GES pronounced guess is described. GES, which is written in Prolog, performs logic extraction from transistor netlists, identification of logic errors within and between components, and generation of VHDL. The input to GES consists of a transistor netlist using format from extract in magic. Logic extraction has been performed, on transistor netlists extracted from design layouts in magic, up to the level of 32-bit adders and 32-bit registers. GES reports typical errors in the construction and interconnection of components. An error-report identifies the component and specifies its location within the magic layout, making it easy to locate the offending circuitry. GES also provides a hierarchical VHDL description of the layout-design that is verified to be free of a large class of design errors. RH

Subject Categories:

  • Computer Programming and Software

Distribution Statement:

APPROVED FOR PUBLIC RELEASE