Accession Number:

ADA229706

Title:

Systolic Signal Processor/High Frequency Direction Finding

Descriptive Note:

Final test rept. FY 1989-FY 1990,

Corporate Author:

NAVAL OCEAN SYSTEMS CENTER SAN DIEGO CA

Personal Author(s):

Report Date:

1990-10-01

Pagination or Media Count:

26.0

Abstract:

This report documents the feasibility of hosting computationally intensive signal processing algorithms on a systolic array architecture. The practicality of such hosting is demonstrated through use of the High Speed Systolic Array Processor HiSSAP testbed and a high frequency direction finding algorithm. Systolic architectures provide a viable alternative to using traditional computer hosts for signal processing application requiring massive quantities of matrix-based computational throughput. The systolic implementations of a four-channel finite impulse responses FIR filter and multiple signal classification MUSIC direction of arrival estimator yielded results consistent with theoretical models. The tests conducted on the HiSSAP testbed demonstrated the feasibility of experimental data produced by both an analytical model and an antenna simulator within a controlled laboratory signal environment. The scope of this investigation should be expanded to include processing of actual off-the-air high frequency radio signals. This advanced level of testing can more realistically estimate the essential design specifications for a proper systolic host for adaptive signal processing algorithms. KR

Subject Categories:

  • Computer Hardware
  • Radio Communications

Distribution Statement:

APPROVED FOR PUBLIC RELEASE