Design and Fabrication of GaAs Mask Programmable Functions and Logic Array. Addendum
Final rept. 24 Jun 1983-30 Sep 1984
ROCKWELL INTERNATIONAL THOUSAND OAKS CA MICROELECTRONICS RESEARCH AND DEVELOPMENT CENTER
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The circuit elements designed for the Phase IIA effort of this program were reported on the LSIVLSI Ion Implanted Planar GaAs IC Processing Semi-Annual Technical Report. Data from the above report and other sources are included within this document for continuity without reference to previously submitted information. Circuit designs were implemented using three basic approaches which included mask programmable functions, storage logic arrays and custom designs. Included with the circuit elements were numerous test structures for collection of parametric and processing data.
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