Accession Number:

ADA220711

Title:

A Fully Testable CMOS Asynchronous Counter

Descriptive Note:

Technical rept.

Corporate Author:

WASHINGTON UNIV SEATTLE NORTHWEST LAB FOR INTEGRATED SYSTEMS

Personal Author(s):

Report Date:

1989-10-01

Pagination or Media Count:

40.0

Abstract:

A testable design for an asynchronous n-bit Complementary Metal Oxide Semiconductors counter is presented, with test inputs that provide full coverage for stuck-at and stuck-open faults. Test time is shown to be On, where the counter outputs are not observable, compared to On squared time for a synchronous counter. There are three control signals required for the testable counter as opposed to one reset signal for the base counter. The testable counter incorporates a scan path, utilizing the state storage in the counter cells, whereby the counter is converted into an n-bit master-slave asynchronous shift register with the counters request input also being used as the shift register input. The only observable outputs are the acknowledge and carry-out request signals. The counter utilizes two-cycle transition signaling and guarantees that new output values are available before acknowledge is toggled. Two 16 bit counters, one base design and one scan-based design, are currently in fabrication 2.0 micron n-well CMOS and will be used to empirically verify the analysis. Splice3 simulations indicate the counter will run at an average speed of approximately 50 MHz. When compared to the base cell, the testable design is achieved with a 15 increase in transistor count from 52 to 60 an increase in chip area of approximately 6 and a reduction in circuit speed of 7.1 based on Splice3 simulation. kr

Subject Categories:

  • Electrical and Electronic Equipment

Distribution Statement:

APPROVED FOR PUBLIC RELEASE