Final Evaluation of MIPS M/500
CARNEGIE-MELLON UNIV PITTSBURGH PA SOFTWARE ENGINEERING INST
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In response to a request from the DoD, an analysis of a Reduced Instruction Set Computer RISC processor, the MIPS M500, was performed. All aspects of processor capabilities and support software were evaluated, tested, and compared to familiar Complex Instruction Set Computer CISC architectures. In all cases, the RISC computer and its support software performed better than a comparable CISC computer. This report provides the general and specific results of these analyses, along with the recommendation that the DoD and other government agencies seriously consider this or other RISC architectures as a highly viable and attractive alternative to the more familiar but less efficient CISC architectures.
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