Fault Tolerant Multiprocessors and VLSI-Based Systems
Final rept. 15 Feb 1987-15 Feb 1988
MASSACHUSETTS UNIV AMHERST
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Two significant aspects of fault-tolerant computing were the focus of this project. Concurrent research was carried out as well in the areas of fault- tolerant testable VLSI system design and fault-tolerant multiprocessor design. A novel concept for testable RAM designs was developed, too, allowing for the design of large RAMs with built-in test capabilities. Such a testability feature is, in fact, an integral part of the design, not added on adhoc, and as such, is the subject of a patent application filed by the U.S. Air Force. The second major focus of research concentrated on the development of fault-tolerant multiprocessor topologies. It was demonstrated that DeBruijn multiprocessor networks provide a naturally fault-tolerant robust interconnection network. The attractive feature of these networks includes their ability to provide fault- tolerance in a wide variety of applications. Also developed was a new topology, termed Flip Trees, which provides certain optimal fault-tolerant properties. Finally, a practical perspective on distributed agreement algorithms was formulated, which can admit a large variety of faults.
- Electrical and Electronic Equipment
- Computer Hardware