Design of a Systolic VLSI Convolution Processor
DEFENCE RESEARCH ESTABLISHMENT VALCARTIER (QUEBEC)
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This report describes the design and implementation of a systolic convolution processor. It uses a number of bit-serial processors, each operating on 8-bit signed coefficients and 8-bit positive pixel intensities. The processing time is independent of the coefficient array size due to the architecture selected. Overflow detection and output scaling capabilities are provided for autonomous applications. Two processors were placed on a CMOS custom integrated circuit using 5 micron design rules. Simulation results were used to estimate the processing time to be under 0.5 s for a 512 x 512 pixel image. Canada.
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