Accession Number:

ADA207228

Title:

The Parallel Decomposition and Implementation of an Integrated Circuit Global Router

Descriptive Note:

Corporate Author:

STANFORD UNIV CA COMPUTER SYSTEMS LAB

Personal Author(s):

Report Date:

1987-01-01

Pagination or Media Count:

8.0

Abstract:

Better quality automatic layout of integrated circuit can be obtained by combining the placement and routing phases so that routing is used as the cost function for placement optimization. Conventional routers are too slow to make this feasible, and so this paper presents a parallel decomposition and implementation of an integrated circuit global router. The LocusRoute router is divided into three orthogonal axes of parallelism routing several wires at once, routing segments of a wire in parallel, and dividing up the potential routes of a segment among different processors to be evaluated. The implementation of two of these approaches achieve significant speedup - wire-by- wire parallelism attains speedups from 6.9 to 13.6 using sixteen processors, and route-by-route achieves up to 4.6 using eight processors. When combined, these approaches can potentially provide speedups of as much as 55 times.

Subject Categories:

  • Electrical and Electronic Equipment
  • Computer Programming and Software

Distribution Statement:

APPROVED FOR PUBLIC RELEASE