Accession Number:

ADA196526

Title:

Transistor Sizing in the Design of High-Speed CMOS (Complementary-Symmetry Metal-Oxide-Semiconductor) Super Buffers

Descriptive Note:

Master's thesis

Corporate Author:

NAVAL POSTGRADUATE SCHOOL MONTEREY CA

Personal Author(s):

Report Date:

1988-03-01

Pagination or Media Count:

146.0

Abstract:

An algorithm for sizing transistors for static Complementary-symmetry Metal-Oxide-Semiconductor CMOS integrated circuit logic design using silicon gate enhancement mode Field-Effect Transistors FET is derived and implemented in software. The algorithm is applied to the mask level hardware design of a three micron minimum feature size p well high-speed super buffer. A software representation of the super buffer can be used for the automated design of custom Very-Large-Scale Integrated VLSI circuits. Keywords MacPITTS Silicon compiler CMOS VLSI Super buffer Transistor sizing and High-Speed CMOS.

Subject Categories:

  • Electrical and Electronic Equipment
  • Solid State Physics

Distribution Statement:

APPROVED FOR PUBLIC RELEASE