Transistor Sizing in the Design of High-Speed CMOS (Complementary-Symmetry Metal-Oxide-Semiconductor) Super Buffers
NAVAL POSTGRADUATE SCHOOL MONTEREY CA
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An algorithm for sizing transistors for static Complementary-symmetry Metal-Oxide-Semiconductor CMOS integrated circuit logic design using silicon gate enhancement mode Field-Effect Transistors FET is derived and implemented in software. The algorithm is applied to the mask level hardware design of a three micron minimum feature size p well high-speed super buffer. A software representation of the super buffer can be used for the automated design of custom Very-Large-Scale Integrated VLSI circuits. Keywords MacPITTS Silicon compiler CMOS VLSI Super buffer Transistor sizing and High-Speed CMOS.
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