Evaluation of Hardware Architectures for HF Antenna Arrays
Final rept. May 1986-May 1987
KANSAS UNIV CENTER FOR RESEARCH INC LAWRENCE TELECOMMUNICATIONS AND INFORMATION SCIENCES LAB
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A variety of hardware architectures can be used for the implementation of HF adaptive signal processing algorithms. The purpose of this study is to evaluate various hardware structures, enumerate their advantages and disadvantages relative to the HF adaptive array problem, and to recommend the architectures best suited to the adaptive HF array systems. The hardware structures are compared based upon complexity which is determined by issues such as computational bounds, input requirements and characteristics of hardware structures. This evaluation is performed in a hierarchical manner. Application of general microprocessor technology is considered first. Integrated circuits tailored for digital signal processing applications is investigated next. Finally VLSI signal processing technology is considered. Included here are Systolic and Wavefront architectures.
- Radio Communications