Accession Number:

ADA193521

Title:

Systolic Array Fault Tolerance Performance Analysis.

Descriptive Note:

Summary rept.,

Corporate Author:

NAVAL UNDERWATER SYSTEMS CENTER NEW LONDON CT NEW LONDON LAB

Personal Author(s):

• Choinski, T. C.
• Leonhardt, M. H.

Report Date:

1988-04-05

Pagination or Media Count:

56.0

Abstract:

The reliability performance of six different systolic array fault tolerance techniques are determined and compared in terms of mean time between failure MTBF. The six techniques include redundant arrays, companion processors, sequential row elimination SRE, alternate row and column elimination ARCE, virtual arrays, and tree based architectures. The results demonstrate the importance of the switching function failure rate in achieving theoretical capability. Virtual arrays were found to have the best theoretical potential for improving the reliability of systolic arrays when high throughput is required. All techniques provided comparable performance for low throughput levels. The potential application of graceful degradation techniques to the minimum variance distortionless response MVDR adaptive beamforming algorithm is discussed. Keywords Adaptive beamforming Fault tolerance Reconfigurable architectures Reliability Systolic Arrays.

Descriptors:

• *BEAM FORMING
• *COMPUTER ARCHITECTURE
• ADAPTIVE SYSTEMS
• ALGORITHMS
• ARRAYS
• DEGRADATION
• DISTORTION
• ELIMINATION
• FAILURE
• FUNCTIONS
• HIGH RATE
• FAULT TOLERANT COMPUTING
• RATES
• REDUNDANCY
• RELIABILITY
• RESPONSE
• SEQUENCES
• SWITCHING
• THROUGHPUT
• VARIATIONS

Subject Categories:

• Computer Programming and Software

Distribution Statement:

APPROVED FOR PUBLIC RELEASE