Accession Number:

ADA191912

Title:

High-Speed Systolic Array Testbed.

Descriptive Note:

Professional paper for Nov 86,

Corporate Author:

NAVAL OCEAN SYSTEMS CENTER SAN DIEGO CA

Personal Author(s):

• Loughlin, J. P.

Report Date:

1987-10-01

Pagination or Media Count:

5.0

Abstract:

Naval Ocean Systems Center has investigated the potential of the systolic architecture for signal processing applications since the concept was introduced by H.T. Kung in 1978. This highly parallel architecture of nearest neighbor data communications and repeated processing node structure promises a favorable marriage of VLSI wafer scale integration and matrix based signal processing algorithms. The successful merging of the technology with the mathematical concepts of eigenvector decomposition, signle value decomposition, or orthogonal factorization necessitates a careful study of a large number of architectural issues. Functional factors associated with the design of a systolic processing element of the candidate applications or numerical stability of the algorithms used require computations in fixed point and integar format or the architecturally more complex and slower floating and point format. The relationship of inputoutput data flow rate and management and the internal computational speed must be studied in assessing the complexity of the processing element.

Descriptors:

• *ARCHITECTURE
• *NODES
• *PROCESSING EQUIPMENT
• *SIGNAL PROCESSING
• *WAFERS
• ALGORITHMS
• COMPUTATIONS
• COMPUTER ARCHITECTURE
• DECOMPOSITION
• EIGENVECTORS
• FLOATING BODIES
• FORMATS
• INTEGRATION
• INTERNAL
• MARRIAGE
• MATHEMATICS
• NUMERICAL ANALYSIS
• ORTHOGONALITY
• PARALLEL ORIENTATION
• PROCESSING
• RATES
• SCALE
• STABILITY
• TEST BEDS

Subject Categories:

• Electrical and Electronic Equipment
• Computer Hardware

Distribution Statement:

APPROVED FOR PUBLIC RELEASE