Accession Number:

ADA191770

Title:

Architecture of the Systolic Linear Algebra Parallel Processor (SLAPP)

Descriptive Note:

Corporate Author:

NAVAL OCEAN SYSTEMS CENTER SAN DIEGO CA

Personal Author(s):

• Symanski, J. J.

Report Date:

1986-08-01

Pagination or Media Count:

6.0

Abstract:

This paper will present preliminary concepts for the design of a systolic array of processors specifically aimed at efficient implementation of a core set of matrix operations consisting of matrix multiplication, QRD, SVD and generalized SVD. The algorithms to be implemented will be discussed briefly. Concepts for efficient implementation of the algorithms will be presented along with future plans.

Descriptors:

• *COMPUTER ARCHITECTURE
• *PARALLEL PROCESSORS
• CORES
• LINEAR ALGEBRA
• MULTIPLICATION
• FLOATING POINT OPERATION
• SIGNAL PROCESSING
• ALGORITHMS

Subject Categories:

• Computer Hardware

Distribution Statement:

APPROVED FOR PUBLIC RELEASE