Architecture of the Systolic Linear Algebra Parallel Processor (SLAPP)
NAVAL OCEAN SYSTEMS CENTER SAN DIEGO CA
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This paper will present preliminary concepts for the design of a systolic array of processors specifically aimed at efficient implementation of a core set of matrix operations consisting of matrix multiplication, QRD, SVD and generalized SVD. The algorithms to be implemented will be discussed briefly. Concepts for efficient implementation of the algorithms will be presented along with future plans.
- Computer Hardware