Design of the Detector II: A CMOS Gate Array for the Study of Concurrent Error Detection Techniques.
STANFORD UNIV CA CENTER FOR RELIABLE COMPUTING
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For some applications of computer systems, errors have to be detected concurrently with normal operation. This is typically done by concurrent error detection CED circuits. Since about 90 of errors in computer systems are caused by temporary failures, CED schemes have to effectively detect errors caused by temporary failures. Most CED schemes are designed with the assumption that errors are caused by events that can be modelled as single-stuck faults. There is a growing body of evidence which suggests that the single stuck-fault model does not model temporary failures very well. This report describes the Detector II, a circuit which was designed to study concurrent error detection schemes experimentally. The purpose of the study is to find out how well the different schemes perform in the presence of real temporary failures, and to gain more knowledge of temporary failures in the process. This will also lead to better models for temporary failures. The circuit was implemented as a CMOS gate array fabricated by Fairchild Gate Array, Milpitas, California. The circuit consists of approximately 2400 equivalent gates and is packaged in a 121 pin ceramic pin-grid array package.
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