Investigation of a Hybrid Wafer Scale Integration Technique that Mounts Discrete Integrated Circuit Die in a Silicon Substrate.
AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH SCHOOL OF ENGINEERING
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This study investigates a hybrid method of Wafer Scale Integration WSI which involves mounting discrete integrated circuit die into etched wells of a silicon wafer substrate, aligning the top surfaces of both the die and the silicon substrate, planarizing the gap between the die and the substrate, applying a conformal, dielectric smoothing layer, and finally, interconnecting the die utilizing a thin-film metallization conductor pattern. The study establishes a fabrication process by which functional integrated circuit die can be close-mounted and reliably interconnected with relatively low-loss conductors. The study is composed of four phases. The first phase is the Wet Orientation Directed Etching WODE study which investigated the suitability of two silicon orientations and three etchants for creating the die wells in the support substrate. The second phase was the Die Attach Adhesive DAA study which investigated the performance of several hybrid circuit attachment adhesives for mounting the die in the wells of the substrate. The third phase involved the preparation of final samples for electrical performance evaluation.
- Solid State Physics
- Electrical and Electronic Equipment