MIPS-X Instruction Set and Programmer's Manual.
STANFORD UNIV CA COMPUTER SYSTEMS LAB
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This manual describes the visible architecture of the MIPS-X processor and the timing information required to execute correct programs. MIPS-X is a pipelined processor that has no hardware interlocks. Therefore, the software system is responsible for keeping track of the timing of the instructions. The processor has a loadstore architecture and supports a very small number of instructions. The instruction set of the processor will be described. The processor supports two types of coprocessor interfaces. One interface is dedicated to the floating point unit and the other will support up to 7 other compressors. These instructions will also be described.
- Computer Programming and Software
- Computer Hardware