Modeling and Simulation of the WFTA (Winograd Fourier Transform Algorithm) 16 PFA (Prime Factor Algorithm) Processor Using the VHSIC (Very High Speed Integrated Circuit) Hardware Description Language. Volume 1.
AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH SCHOOL OF ENGINEERING
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The VHSIC Hardware Description Language VHDL is applied to the problem of modeling and simulating VLSI CMOS components of the WFTA 16 PFA processor. The 16-point PFA processor is one of three PFA processors under design and development for the implementation of the 4080-point PFA pipeline processor by the VLSI design group at the Air Force Institute of Technology. The PFA processor is modeled by applying the hierarchical facilities of the VHDL language to form the top level register component descriptions from combinations of the primary building block hardware element descriptions. Two simple VHDL simulations are performed using the beta test versions of the VHDL simulator and support environment. The simple component simulations are performed on a VHDL Behavioral description of the Parallel-In, Serial-Out register cell and a VHDL structural description of a dynamic MSFF. Keywords Thesis Digital simulation Signal processing.
- Theoretical Mathematics