Accession Number:

ADA175735

Title:

The Synergistically Integrated Reliability Architecture: A Reliability Analysis of an Ultra-Reliable Fault Tolerant Computer Design.

Descriptive Note:

Master's thesis,

Corporate Author:

NAVAL POSTGRADUATE SCHOOL MONTEREY CA

Personal Author(s):

Report Date:

1986-09-26

Pagination or Media Count:

137.0

Abstract:

This thesis develops a Semi-Markov reliability model for the Synergistically Integrated Reliability SIR computer architecture. The SIR architecture is an advanced hybrid redundancy scheme that combines several current reliability techniques to achieve hardware and software reliability. These methods include hybrid redundancy, N-Version programming and source congruent data interchange. The architecture is designed to support active control systems in the aircraft avionics industry as well as the bus controller requirements for the Dispersed Sensor Processor Mesh DSPM system for ultra-reliable computer communications. The paper also develops high level algorithms for fault detection, location, and configuration management within the SIR system. The reliability model integrates the hardware design, the hybrid redundancy philosophy, and the operating constraints of an active control system into a single reliability model. Specific models are developed for the 3, 4, and 5 processor cases of the SIR architecture and plots of the system reliability vs mission time are generated using the SURE Reliability Analysis Program.

Subject Categories:

  • Electrical and Electronic Equipment
  • Computer Programming and Software
  • Computer Hardware
  • Manufacturing and Industrial Engineering and Control of Production Systems

Distribution Statement:

APPROVED FOR PUBLIC RELEASE