Test Procedures and Testable-Design Procedures for CMOS LSI/VLSI Circuits.
Final rept. 1 Apr 84-30 Sep 86,
IOWA UNIV IOWA CITY
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The goals of the research on CMOS logic circuits, being performed under the support of the U.S. Army Research Office are i-Investigate the most probable failure modes in CMOS logic circuits and derive fault models that can be used to analyze CMOS logic circuits. Using the derived fault models design procedures for fault diagnosis in CMOS logic circuits, and ii-Develop methods to design logic circuits to facilitate fault diagnosis.
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